4-269 file number 2314.3 caution: these devices are sensitive to electrostatic discharge; follow proper esd handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 IRFD110 1a, 100v, 0.600 ohm, n-channel power mosfet this n-channel enhancement mode silicon gate power ?eld effect transistor is an advanced power mosfet designed, tested, and guaranteed to withstand a speci?ed level of energy in the breakdown avalanche mode of operation. all of these power mosfets are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. these types can be operated directly from integrated circuits. formerly developmental type ta17441. features ? 1a, 100v ?r ds(on) = 0.600 w ? single pulse avalanche energy rated ? soa is power dissipation limited ? nanosecond switching speeds ? linear transfer characteristics ? high input impedance ? related literature - tb334 guidelines for soldering surface mount components to pc boards symbol packaging hexdip ordering information part number package brand IRFD110 hexdip IRFD110 note: when ordering, use the entire part number. g d s source gate drain data sheet july 1999
4-270 absolute maximum ratings t c = 25 o c, unless otherwise speci?ed IRFD110 units drain to source breakdown voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ds 100 v drain to gate voltage (r gs = 20k w) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 100 v continuous drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d 1.0 a pulsed drain current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 8.0 a gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 20 v maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .p d 1.0 w linear derating factor (see figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.008 w/ o c single pulse avalanche energy rating (note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as 19 mj operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j ,t stg -55 to 150 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio nofthe device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. note: 1. t j = 25 o c to 125 o c. electrical speci?cations t c = 25 o c, unless otherwise speci?ed parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 m a, v gs = 0v (figure 9) 100 - - v gate threshold voltage v gs(th) v gs = v ds , i d = 250 m a 2.0 - 4.0 v zero gate voltage drain current i dss v ds = rated bv dss , v gs = 0v - - 25 m a v ds = 0.8 x rated bv dss , v gs = 0v, t c = 125 o c - - 250 m a on-state drain current (note 2) i d(on) v ds > i d(on) x r ds(on)max , v gs = 10v 1.0 - - a gate to source leakage current i gss v gs = 20v - - 100 na drain to source on resistance (note 2) r ds(on) i d = 0.8a, v gs = 10v (figures 7, 8) - 0.5 0.6 w forward transconductance (note 2) g fs v ds > i d(on) x r ds(on)max , i d = 0.8a (figure 11) 0.8 1.2 - s turn-on delay time t d(on) v dd = 0.5 x rated bv dss , i d ? 1.0a, r g = 9.1 w, r l = 50 w mosfet switching times are essentially independent of operating temperature -1020ns rise time t r -1525ns turn-off delay time t d(off) -1525ns fall time t f -1020ns total gate charge (gate to source + gate to drain) q g(tot) v gs = 10v, i d ? 1.0a, v ds = 0.8 x rated bv dss, i g(ref) = 1.5ma (figure 13) gate charge is essentially independent of operating temperature - 5.0 7.0 nc gate to source charge q gs - 2.0 - nc gate to drain miller charge q gd - 3.0 - nc input capacitance c iss v gs = 0v, v ds = 25v, f = 1mhz (figure 10) - 135 - pf output capacitance c oss -80- pf reverse transfer capacitance c rss -20- pf internal drain inductance l d measured from the drain lead, 2mm (0.08in) from package to center of die modified mosfet symbol showing the internal devices inductances - 4.0 - nh internal source inductance l s measured from the source lead, 2mm (0.08in) from header to source bonding pad - 6.0 - nh thermal resistance junction to ambient r q ja free air operation - - 120 o c/w l s l d g d s IRFD110
4-271 source to drain diode speci?cations parameter symbol test conditions min typ max units continuous source to drain current i sd modified mosfet symbol showing the integral reverse p-n junction diode - - 1.0 a pulse source to drain current (note 4) i sdm - - 8.0 a source to drain diode voltage (note 2) v sd t j = 25 o c, i sd = 1.0a, v gs = 0v (figure 12) - - 2.5 v reverse recovery time t rr t j = 150 o c, i sd = 1.0a, di sd /dt = 100a/ m s - 100 - ns reverse recovery charge q rr t j = 150 o c, i sd = 1.0a, di sd /dt = 100a/ m s - 0.2 - m c notes: 2. pulse test: pulse width 300 m s, duty cycle 2%. 3. v dd = 25v, starting t j = 25 o c, l = 28.5mh, r g = 25 w, peak i as = 1.0a. 4. repetitive rating: pulse width limited by maximum junction temperature. typical performance curves unless otherwise speci?ed figure 1. normalized power dissipation vs ambient temperature figure 2. maximum continuous drain current vs ambient temperature figure 3. forward bias safe operating area figure 4. output characteristics g d s t a , ambient temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 t a , ambient temperature ( o c) 50 75 100 25 150 1.0 0.8 0.6 0 0.4 i d, drain current (a) 0.2 125 v ds , drain to source voltage (v) 1 i d , drain current (a) 100 0.1 10 1 0.01 1ms 10ms 100ms 100 m s limited by r ds(on) area may be operation in this dc 10 t j = max rated i d , drain current (a) 0 10203040 1 2 3 4 5 50 v ds , drain to source voltage (v) 0 v gs = 4v v gs = 5v v gs = 7v pulse duration = 80 m s v gs = 10v v gs = 8v v gs = 6v v gs = 9v duty cycle = 0.5% max IRFD110
4-272 figure 5. saturation characteristics figure 6. transfer characteristics note: heating effect of 2 m s pulse is minimal. figure 7. drain to source on resistance vs gate voltage and drain current figure 8. normalized drain to source on resistance vs junction temperature figure 9. normalized drain to source breakdown voltage vs junction temperature figure 10. capacitance vs drain to source voltage typical performance curves unless otherwise speci?ed (continued) i d , drain current (a) 01 2 3 4 1 2 3 4 5 5 v ds , drain to source voltage (v) 0 v gs = 9v v gs = 4v v gs = 5v v gs = 7v v gs = 10v v gs = 8v v gs = 6v pulse duration = 80 m s duty cycle = 0.5% max 5 i d(on) , on-state drain current (a) v gs , gate to source voltage (v) 4 3 2 0 8 6 4 2 010 1 t j = 25 o c t j = 125 o c t j = -55 o c pulse duration = 80 m s duty cycle = 0.5% max v ds > i d(on) x r ds(on)max 0 1.0 2.0 246 r ds(on) , drain to source i d , drain current (a) 8 0 0.5 1.5 v gs = 10v v gs = 20v on resistance ( w ) duty cycle = 0.5% max 2 m s pulse test normalized drain to source 2.5 1.5 1.0 0.5 0 -60 -20 40 t j , junction temperature ( o c) 120 140 2.0 80 100 60 20 0 -40 on resistance pulse duration = 80 m s duty cycle = 0.5% max v gs = 10v, i d = 0.8a 1.25 0.95 0.85 0.75 -60 -20 20 t j , junction temperature ( o c) normalized drain to source breakdown voltage 60 100 140 1.05 1.15 -40 0 40 80 120 i d = 250 m a 500 100 0 0 20 50 c, capacitance (pf) 300 v ds , drain to source voltage (v) 400 200 10 30 c iss c oss c rss 40 v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss ? c ds + c gd IRFD110
4-273 figure 11. transconductance vs drain current figure 12. source to drain diode voltage figure 13. gate to source voltage vs gate charge test circuits and waveforms figure 14. unclamped energy test circuit figure 15. unclamped energy waveforms typical performance curves unless otherwise speci?ed (continued) i d , drain current (a) g fs , transconductance (s) 01 2 34 0.8 1.5 2.4 3.2 4.0 5 0 t j = -55 o c t j = 25 o c t j = 125 o c pulse duration = 80 m s duty cycle = 0.5% max 0 0.6 1.0 1.4 1.6 0.2 0.1 1.0 2 i sd , source to drain current (a) v sd , source to drain voltage (v) 10 0.4 1.2 t j = 25 o c t j = 150 o c 5 5 2 1.8 2.0 0.8 pulse duration = 80 m s duty cycle = 0.5% max q g , gate charge (nc) v gs , gate to source (v) 04610 5 15 20 i d = 1a 10 0 28 v ds = 80v v ds = 50v v ds = 20v t p v gs 0.01 w l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 IRFD110
4-274 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 figure 16. switching time test circuit figure 17. resistive switching waveforms figure 18. gate charge test circuit figure 19. gate charge waveforms test circuits and waveforms (continued) v gs r l r g dut + - v dd t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 0.3 m f 12v battery 50k w v ds s dut d g i g(ref) 0 (isolated v ds 0.2 m f current regulator i d current sampling i g current sampling supply) resistor resistor same type as dut q g(tot) q gd q gs v ds 0 v gs v dd i g(ref) 0 IRFD110
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